Characterization and modeling of SOI RF integrated components

The boom of mobile communications leads to an increasing request of low cost and low power mixed mode integrated circuits. Maturity of SOI technology, and recent progresses of MOSFET's microwave performances, explain the success of silicon as compared to III-V technologies for low-cost multigigahertz analog applications. The design of efficient circuits requires accurate, wide-band models for both active and passive elements. Within this frame, passive components fabricated in SOI technologies have been studied, and a physical model of integrated square spiral inductors has been developed. Also, the performances of integrated MOSFETs have been analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) have been proposed and studied from Low to High frequencies. These transistors show very interesting properties for analog, low power, low voltage, and microwave applications. Furthermore, as their fabrication processes are fully CMOS compatible, they allow us to increase the performances of a CMOS technology without any modification of its process, and without extra-cost.(FSA 3)--UCL, 200

Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis

This paper analyzes the frequency dependence of the gate transconductance (G(m)) and output conductance (G(d)) of a DTMOS in 0.25 mum PD SOI MOS technology. Our experimental results demonstrate for the first time that DTMOS devices suffer from a strong degradation of G(m) and G(d) around 1 GHz. An equivalent small-signal circuit is proposed to explain the observed phenomena. The model clearly identifies the non-zero value of the body contact resistance as the source of the G(m) and G(d) degradation. DTMOS stays a promising MOS structure for low power, low voltage high frequency applications. (C) 2004 Elsevier Ltd. All rights reserved

An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics

Asymmetric doped channel metal oxide semiconductor field effect transistors (MOSFETs) have recently been investigated by several authors in bulk and silicon-on-insulator (SOI) technologies as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage rolloff issues in deep sub-micrometer devices. In this paper, the DC and microwave characteristics of the asymmetric doped channel fully depleted (FD) SOI MOSFET are presented and compared to conventional uniformly doped FD SOI MOSFET

An improved multiline analysis for monolithic inductors

This paper presents a new efficient multiline model for monolithic inductors. A preliminary model was developed by Huynen, which divided the spiral in sections of coupled transmission lines whose parameters are calculated by a variational principle. This model has been improved for inductors with high trace width-to-gap ratios and it has been demonstrated to be adequate for predicting S-parameters characterizing the inductor over a wide frequency band, even above its self-resonant frequency. This new design tool is shown to be useful for analyzing and optimizing inductor topologies built on both insulating and semiconducting substrates

Alternative architectures of SOI MOSFET for improving DC and microwave characteristics

DC and high frequency characteristics of innovative SOI MOSFETs such as graded channel and dynamic threshold voltage MOS are presented in this paper. These architectures are very promising for high frequency low power low voltage analog applications.Anglai

Comparison of different extraction methods of small-signal parameters for SOI MOSFETs

For the first time, a comparison is made between different equivalent circuits and different extraction procedures using simulated and measured Silicon-on-Insulator (SOI) MOSFETs. The methods, which will be described, are divided into three categories: the depletion methods, the inversion methods also called cold-FET methods and the saturation methods. Moreover, a novel technique will be presented for the extraction of parasitic capacitances of a MOSFET in deep depletion